This application claims the priority of German Application No. 103 27 116.3, filed Jun. 13, 2003, the disclosure of which is expressly incorporated by reference herein.
The invention relates to a method for time synchronisation of at least two clocks contained in a multiprocessor system.
In a multiprocessor system, such as is used, for example, for the purpose of processing large amounts of data and/or various tasks in real time, one difficulty consists in synchronising the clocks of the individual processors in such a way that they run in like manner, i.e. so that the temporal deviation thereof does not exceed a certain predefined tolerance value. A “clock” in this connection is to be understood to mean a timing-pulse generator or clock-pulse generator in the form of, for example, a “counter” or a “timer” which initially generates a relative—time-indication in the form of a time-stamp, which, however, can be converted to the current time in the style of an absolute-time clock. A “counter” is usually realised by a precise quartz-crystal oscillator which oscillates at a particular frequency that is more or less precise, depending on the quality and type of the quartz crystal. A counter register which is incremented by 1 after each period-length P or after a fraction thereof is usually connected to the quartz crystal. Also similar to the “counter” is the “timer”, which, in contrast, exhibits an additional register in the form of a so-called holding register. After each period-length T of the quartz crystal or after a multiple thereof, the counter register is decremented. As soon as this counter register has been decremented to zero, an interrupt is generated and the counter register is set to the value in the holding register.
A problem is constituted, on the one hand, by a fundamental deviation of the oscillation of the quartz crystal, by the latter “going” too fast or too slowly, and, on the other hand, by a “drifting-away” as a function of temperature. The cycle deviation of a quartz crystal at constant temperature is represented in FIG. 2a); the drifting-away at first in the event of a change of temperature, for example when the processor is starting up, and then a constant cycle deviation at constant temperature, are represented in FIG. 2b).
The invention proceeds from a method for time synchronisation of at least two clocks contained in a multiprocessor system, wherein a first clock having a predetermined clock rate generates consecutive respective time-stamps indicating the time and at least one second clock which has an adjustable clock rate is synchronised with the first clock at certain time intervals.
The object of the invention is to create a method of this type in such a way that a bus by which the processors of the multiprocessor system are connected to one another is loaded as little as possible by the time synchronisation.
By virtue of the invention, a method is created for time synchronisation of at least two clocks contained in a multiprocessor system, wherein a first clock having a predetermined clock rate generates consecutive respective time-stamps indicating the time and at least one second clock which has an adjustable clock rate is synchronised with the first clock at certain time intervals. According to the invention there is provision that a) at predetermined time intervals the relative temporal position of flanks of the first clock and of the second clock representing the transition between two consecutive time-stamps is recorded, that b) from the change in the relative temporal position of the transition flanks of the first clock and of the second clock a correction factor representing the time deviation between the first clock and the second clock is determined, that c) by means of the correction factor representing the time deviation between the first clock and the second clock the clock rate of the second clock is readjusted, wherein the readjustment is of a diminution of the time deviation between the first clock and the second clock, and that d) steps a) to c) are repeated.
According to one aspect of the invention, the temporal position of the transition flanks of the first clock and/or of the second clock can be recorded by polling, by the time-stamp of the clock in question being read out at least twice in succession and by the time-stamps obtained thereby being compared with one another and by the read-out of the time-stamp being repeated until such time as the time-stamp last obtained differs from the previous time-stamp.
According to another aspect of the invention, the change in the temporal position of the transition flanks of the first clock and of the second clock can be recorded by a two-stage flank search, by the time-stamp of the clock in question being read out once before an assumed transition flank between two consecutive time-stamps and once after an assumed transition flank between two consecutive time-stamps and by the time-stamp obtained in each instance being compared with the time-stamp expected for the time of read-out and by this process being continued, wherein i) a concordance both of the time-stamp obtained in the case of read-out before the assumed transition flank with the expected time-stamp and of the time-stamp obtained in the case of read-out after the assumed transition flank with the expected time-stamp is appraised with respect to a correct position of the assumed transition flank, ii) a concordance of the time-stamp obtained in the case of read-out before the assumed transition flank with the expected time-stamp and a concordance of the time-stamp obtained in the case of read-out after the assumed transition flank, but with an earlier time-stamp than that expected, is appraised with respect to a belated position of the assumed transition flank or with respect to a time of read-out that was too early, and iii) a concordance of the time-stamp obtained in the case of read-out after the assumed transition flank with the expected time-stamp and a concordance of the time-stamp obtained in the case of read-out before the assumed transition flank, but with a later time-stamp than that expected, is appraised with respect to a premature position of the assumed transition flank or in the sense of a time of read-out that was too late.
The read-out of the time-stamps can be undertaken in each instance before and after the same assumed transition flank between the same two consecutive time-stamps.
However, the reading of the time-stamps is preferably undertaken in each instance before and after various assumed transition flanks between respective various two consecutive time-stamps, in particular alternately.
It is particularly advantageous to perform the reading of the time-stamps in each instance alternately before and after various assumed transition flanks, which follow one another at equal time intervals.
According to a particularly advantageous embodiment of the invention, there is provision that at the start of the synchronisation process the position of the transition flanks is recorded by polling, by reading out the time-stamp of the clock in question at least twice in succession, comparing the time-stamps thereby obtained with one another and repeating the read-out of the time-stamp until such time as the time-stamp last obtained differs from the previous time-stamp, and that the change in the temporal position is then recorded by a two-stage flank search, by reading out the time-stamp of the clock in question once before an assumed transition flank between two consecutive time-stamps and once after an assumed transition flank between two consecutive time-stamps, comparing the time-stamp obtained in each instance with the time-stamp expected for the time of read-out and continuing this process, wherein i) a concordance both of the time-stamp obtained in the case of read-out before the assumed transition flank with the expected time-stamp and of the time-stamp obtained in the case of read-out after the assumed transition flank with the expected time-stamp is appraised with respect to a correct position of the assumed transition flank, ii) a concordance of the time-stamp obtained in the case of read-out before the assumed transition flank with the expected time-stamp and a concordance of the time-stamp obtained in the case of read-out after the assumed transition flank, but with an earlier time-stamp than that expected, is appraised with respect to a belated position of the assumed transition flank or with respect to a time of read-out that was too early, and iii) a concordance of the time-stamp obtained in the case of read-out after the assumed transition flank with the expected time-stamp and a concordance of the time-stamp obtained in the case of read-out before the assumed transition flank, but with a later time-stamp than that expected, is appraised with respect to a premature position of the assumed transition flank or with respect to a time of read-out that was too late.
There is preferably provision that the correction factor representing the time deviation between the first clock and the second clock is determined by comparison of the temporal spacing between, in each instance, two transition flanks of the first and second clocks corresponding to one another.
According to another preferred embodiment of the method according to the invention, there is provision that the clock rate of the second clock is readjusted in the sense of a diminution of the time deviation between the first clock and the second clock (step c) when at least two consecutive read-out processes have resulted in a time deviation in the same direction with respect to either of a belated position of the assumed transition flanks, or to be more exact, with respect to a read-out that was too early, or with respect to a premature position of the assumed transition flanks, or to be more exact, with respect to a time of read-out that was too late.
In a preferred embodiment of the method according to the invention, the first clock is a central, cyclically accurate clock.
The at least one second clock is preferably an internal clock of a processor contained in the multiprocessor system.
The second, internal clock is preferably a virtual clock generated by software.
The multiprocessor system preferably includes several processors with several second clocks assigned to these processors, which are synchronised with the first clock or by means of the latter.
In this connection it is preferable that the several second clocks are each synchronised with the first clock at various consecutive times.